Each semiconductor integrated circuit (electronic circuit) formed on a semiconductor wafer is subjected to electrical inspection using a tester device before being divided to chips. In this electrical inspection, a probe card is generally interposed between a tester device and semiconductors integrated circuit as a test object, and the probe card transmits inspection signals, response output, and the like between the tester device and the semiconductor integrated circuit.
To be more specific, the probe card has a circular plate form, and includes, at an upper surface periphery thereof, a tester interface part connected to the tester device.
The probe card includes a plurality of probes electrically connected to the tester interface part. Each probe is in contact with an electrode pad of each semiconductor integrated circuit, whereby the semiconductor integrated circuit is electrically connected to the tester through the probe.
Moreover, the probe card includes a wiring board, and a plurality of probes are arranged on one surface of the wiring board. The probes are connected to the tester interface part by a direct wiring path, or through an electronic part (e.g., a relay, a condenser, a resistor, a coil, etc.) provided on an upper surface of the wiring board. Therefore, as the wiring board of such a probe card, a multilayer wiring board is formed.
To achieve a number of wiring paths, a number of vias are arranged on a wiring board of each layer forming a multilayer wiring board. The vias are generally arranged in a latticed pattern with equal pitches in accordance with mounted parts and the like, and the wiring is housed between vias with equal pitch intervals (see FIG. 12).
For example, it is supposed that the via pad 2 is arranged in the conditions that a dimension of a via pad (diameter 2r here) is 0.5 mm, a wiring width w is 0.1 mm, and a pitch interval p of via pads is 0.8 mm, as illustrated in FIG. 13. In such a case, if it is necessary to secure a clearance of 0.05 mm or larger between a via pad and a wiring pattern, one wiring 3 is provided between the via pads 2-1 and 2-2.
Recently, with the narrower pitches between mounted parts, the pitch interval between via pads arranged on each wiring board has been also reduced, which makes it difficult to increase the number of wirings housed between via pads.
When the wiring is housed between via pads arranged in a latticed pattern with equal pitches, a slight clearance may be left in the pitch interval of the via pads, depending on design conditions of a wiring board. In such a case, to improve the wiring housing property, a designer adjusts the arrangement of via pads to increase the number of wirings.
Conventionally, Patent Literature 1 discloses, for example, the method of adjusting the arrangement of via pads. Patent Literature 1 discloses the technology which increases or reduces the pitch intervals in a vertical direction or horizontal direction between via pads in a block area.
Moreover, a designer also adjusts positions of via pads to arbitrary positions to improve the wiring housing property.